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as1153, as1157 dual lvds receiver www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 1 - 16 datasheet 1 general description the as1153, as1157 are dual flow-through lvds (low-voltage differ- ential signaling) receivers which accept lvds differential inputs and convert them to lvcmos outputs. the receivers are perfect for low- power low-noise applications requiring high signaling rates and reduced emi emissions. the devices are guaranteed to receive data at speeds up to 260mbps (130mhz) over controlled impedance media of approxi- mately 100 . supported transmission media are pcb traces, back- planes, and cables. the as1153, as1157 features integrated parallel termination resis- tors (nominally 107 ), which eliminate the requirement for discrete termination resistors, and reduce stub lengths. the as1153, as1157 uses high impedance inputs and requires an external termination resistor when used in a point-to-point connection. the integrated failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted. all inputs conform to the ansi tia/eia- 644 lvds standards. flow- through pinout simplifies pc board layout and reduces crosstalk by separating the lvds inputs and lvcmos outputs. the devices are available in a 8-pin soic package. figure 1. as1153, as1157 - block diagram 2 key features flow-through pinout guaranteed 260mbps data rate 300ps pulse skew (max) conform to ansi tia/eia-644 lvds standards single +3.3v supply operating temperature range: -40c to +85oc failsafe circuit integrated termination (as1157) 8-pin soic package 3 applications digital copiers, laser printers, cellular phone base stations, add/ drop muxes, digital cross-connec ts, dslams, network switches/ routers, backplane interconnect, clock distribution computers, intelligent instruments, controllers, critical microprocessors and microcontrollers, power monitoring, and portable/battery-powered equipment. as1153/57 in1- in1+ in2+ in2- vcc out1 out2 gnd
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 2 - 16 as1153, as1157 datasheet - pinout and packaging 4 pinout and packaging pin assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin number pin name description 1in1- inverting differential receiver input 2in1+ noninverting differential receiver input 3in2+ noninverting differential receiver input 4in2- inverting differential receiver input 5gnd ground 6out2 lvcmos/lvttl receiver output 7out1 lvcmos/lvttl receiver output 8vcc power-supply input. bypass v cc to gnd with 0.1f and 0.001f ceramic capacitors. vcc out1 out2 gnd in1- in1+ in2+ in2- as1153/57 1 2 3 4 8 7 6 5
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 3 - 16 as1153, as1157 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters vcc to gnd -0.3 5.0 v inx+, inx- to gnd -0.3 5.0 v outx+, outx- to gnd -0.3 vcc + 0.3 v electrostatic discharge electrostatic discharge hbm +/- 4 kv norm: mil 883 e method 3015, inx+, inx- temperature ranges and storage conditions thermal resistance ja 128 oc/w typical 4-layer application junction temperature +150 oc storage temperature range -55 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level 1 represents a max. floor life time of unlimited
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 4 - 16 as1153, as1157 datasheet - electrical characteristics 6 electrical characteristics dc electrical characteristics v cc = +3.0 to +3.6v, differential input voltage |v id | = +0.1 to +1.0v, common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|,t amb = -40c to +85oc. typical values are at v cc = +3.3v, t amb = +25oc (unless otherwise specified). table 3. dc electrical characteristics parameter symbol conditions min typ max unit operating temperature range t amb -40 +85 c lvds inputs (in x +, in x -) differential input high threshold v th 100 mv differential input low threshold v tl -100 mv input current 1 ( as1153 ) 1. current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v th , v tl , and v id . i in x +, i in x - 0.1v |v id | 0.6v -20 20 a 0.6v |v id | 1.0v -25 25 a differential input resistance (as1157) r diff v cc = 3.6v or 0, figure 18 on page 9 90 107 132 differential input resistance (as1153) r diff 2 2. 2xr in = r diff v cc = 3.6v or 0, figure 18 on page 9 40 100 k lvcmos/lvttl outputs (out x ) output high voltage (table 5) v oh i oh = -4.0ma (as1153) open, undriven short, or undriven 100 parallel termination 2.7 3.2 v v id = +100mv 2.7 3.2 i oh = -4.0ma ( as1157 ) open or undriven short 2.7 3.2 v id = +100mv 2.7 3.2 output low voltage v ol i ol = +4.0ma, v id = -100mv 0.1 0.25 v output short-circuit current 3 3. short only one output at a time. do not exceed the absolute maximum junction temperature specification. note: all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical qual ity control) methods. i os v id = 100mv, v out x = 0 15 ma supply supply current i cc inputs open 0.6 2 ma |v id | = 200mv 4.5 8 ma
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 5 - 16 as1153, as1157 datasheet - electrical characteristics ac electrical characteristics v cc = +3.0 to +3.6v, c load = 10pf, differential input voltage |v id | = 0.2 to 1.0v, common-mode voltage v cm = |v id /2| to 2.4v -|v id /2|, input rise and fall time = 1ns (20 to 80%), input frequency = 100mhz, t amb = -40 to +85oc. typical values are at v cc = +3.3v, v cm = 1.2v, |v id | = 0.2v, t amb = +25oc (unless otherwise specified). 1, 2 notes: 1. ac parameters are guaranteed by design and characterization. 2. c l includes scope probe and test jig capacitance. 3. t skd1 is the magnitude difference of differential propagation delays in a channel. t skd1 = |t phld - t plhd |. 4. t skd2 is the magnitude difference of the t plhd or t phld of one channel and the t plhd or tphld of any other channel on the same device. 5. t skd3 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same v cc and within 5oc of each other. 6. t skd4 is the magnitude difference of any differential propagation delays between devices operating over rated conditions. 7. f max generator output conditions: a. rise time = fall time = 1ns (0 to 100%) b. 50% duty cycle c. voh = +1.3v d. vol = +1.1v 8. output criteria: a. duty cycle = 60% to 40% b. v ol = 0.4v (max) c. v oh = 2.7v (min) d. load = 10pf table 4. ac electrical characteristics parameter symbol conditions min typ max unit differential propagation delay high-to-low t phld figure 20 on page 11 and figure 21 on page 12 11.83.1ns differential propagation delay low-to-high t plhd figure 20 on page 11 and figure 21 on page 12 11.83.1ns differential pulse skew (t phld - t plhd ) 3 t skd1 figure 20 on page 11 and figure 21 on page 12 250 600 ps differential channel-to-channel skew 4 t skd2 figure 20 on page 11 and figure 21 on page 12 600 ps differential part-to-part skew 5 t skd3 figure 20 on page 11 and figure 21 on page 12 0.8 ns differential part-to-part skew 6 t skd4 figure 20 on page 11 and figure 21 on page 12 1.5 ns rise time t tlh figure 20 on page 11 and figure 21 on page 12 0.4 1.0 ns fall time t thl figure 20 on page 11 and figure 21 on page 12 0.4 1.0 ns maximum operating frequency 7, 8 f max all channels switching 130 160 mhz
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 6 - 16 as1153, as1157 datasheet - typical operating characteristics 7 typical operating characteristics v cc = +3.3v, v cm = +1.2v, |v id | = 0.2v, c load = 10pf, t amb = +25oc, unless otherwise noted. figure 3. supply current vs. frequency figure 4. supply current vs. temperature figure 5. diff. threshold voltage vs. v cc figure 6. output short-circuit current vs. v cc figure 7. output low voltage vs. v cc figure 8. output high voltage vs. v cc 0 5 10 15 20 -45 -30 -15 0 15 30 45 60 75 90 temperature(c) supply current (ma) . 0 10 20 30 40 50 0 50 100 150 200 250 300 frequency (mhz) supply current (ma) . all channels switching one channel switching f = 100mhz f = 1mhz low to high high to low 0 5 10 15 20 25 30 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) differential output voltage (mv) . 0 20 40 60 80 100 120 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) output short circuit current (ma) . vth vtl 2.7 2.8 2.9 3 3.1 3.2 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) output voltage (v) . 72 72,5 73 73,5 74 74,5 75 3 3,1 3,2 3,3 3,4 3,5 3,6 supply voltage (v) output voltage (mv) .
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 7 - 16 as1153, as1157 datasheet - typical operating characteristics figure 9. differential propagation delay vs. v cc figure 10. differential propagation delay vs. temp. figure 11. differential propagation delay vs. v cm figure 12. differential propagation delay vs. v id figure 13. differential propagation delay vs. load 1.75 1.8 1.85 1.9 1.95 2 2.05 -45 -30 -15 0 15 30 45 60 75 90 temperature(c) diff. propagation delay (ns) . 1.7 1.74 1.78 1.82 1.86 1.9 1.94 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) diff. propagation delay (ns) . t phld t plhd t phld t plhd 0.75 1 1.25 1.5 1.75 2 2.25 0.1 0.5 0.9 1.3 1.7 2.1 2.5 differential-input voltage(v) diff. propagation delay (ns) . 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 00.511.522.5 common-mode voltage(v) diff. propagation delay (ns) . t phld t plhd t phld t plhd 0 0.5 1 1.5 2 2.5 3 10 15 20 25 30 35 40 45 50 capacitive load (pf) diff. propagation delay (ns) . t phld t plhd
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 8 - 16 as1153, as1157 datasheet - typical operating characteristics figure 14. differential pulse skew vs. v cc figure 15. transition time vs. capacitive load figure 16. transition time vs. v cc figure 17. transition time vs. temperature 400 600 800 1000 1200 1400 1600 10 15 20 25 30 35 40 45 50 capacitive load (pf) transition time (ps) . t thl t tlh 0 50 100 150 200 250 300 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) differential pulse skew (ps) . 300 325 350 375 400 425 450 475 -45 -30 -15 0 15 30 45 60 75 90 temperature(c) transition time (ps) . 340 350 360 370 380 390 400 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) transition time (ps) . t tlh t thl t thl t tlh
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 9 - 16 as1153, as1157 datasheet - detailed description 8 detailed description the as1153, as1157 are 260mbps, dual-channel lvds receivers intended for high-speed, point-to-point, low-power applications. ea ch inde- pendent channel accepts and converts an lvds input to an lvttl/lvcmos output. the devices are capable of detecting differential signals from 100mv to 1v within an input voltage range of 0 to 2.4v. the 250 to 450mv differential output of an lvds driver is nomin ally centered around 1.25v. due to the receiver input voltage ra nge, a 1v volt- age shift in the signal relative to the receiver is allowed. thus, a difference in ground references of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated. lvds interface the lvds interface standard is a signaling method defined for point-to-point communication over a controlled-impedance medium a s defined by the ansi tia/eia-644 and ieee 1596.3 standards. the lvds standard uses a lower voltage swing than other common communication stan- dards, resulting in higher data rates, reduced power consumption and emi emissions, and less susceptibility to noise. the devices fully comply with the lvds standard input voltage range of 0 to +2.4v referenced to receiver ground. the as1157 has an integrated termination resistors connected internally across each receiver input. this internal termination s aves board space, eases layout, and reduces stub length compared to an external termination resistor. in other words, the transmission lin e is terminated on the ic. failsafe circuit the devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriv en and shorted. open or undriven terminated input conditions can occur if there is a cable failure or when the lvds driver outputs are high imp edance. a short condition also can occur because of a cable failure. the failsafe circuit of the as1153, as1157 automatically sets the output h igh if any of these conditions are true. the failsafe input circuit (see figure 18) samples the input common-mode voltage and compares it to v cc - 0.3v (nominal). if the input is driven to levels specified in the lvds standards, the input common-mode voltage is less than v cc - 0.3v and the failsafe circuit is not activated. if the inputs are open, undriven and shorted, or undriven and parallel te rminated, there is no input current. in this case, a pullup r esistor in the failsafe circuit pulls both inputs above v cc - 0.3v, activating the failsafe circuit and thus forcing the device output high. figure 18. failsafe input circuit v cc - 0.3v r in2 r in1 r in1 r diff as1157 v cc - 0.3v r in2 r in1 r in1 as1153 in x - out x in x + in x - out x in x + v cc v cc
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 10 - 16 as1153, as1157 datasheet - applications 9 applications figure 19. typical application circuit power-supply bypassing to bypass v cc , use high-frequency surface-mount ceramic 0.1f and 0.001f capacitors in parallel as close to the device as possible, with th e smaller valued capacitor closest to pin v cc . differential traces input trace characteristics can adversely affect the performance of the as1153, as1157. use controlled-impedance pc board traces to match the cable characteristic impedance. the termination resistor must also be mat ched to this characteristic impedance. eliminate reflections and ensure that noise couples as common mode by running differential traces close together. reduce skew by using matched trace lengths. tight skew control is required to minimize emissions and proper data recovery of th e devices. route each channel?s differential signals very close to each other for optimal cancellation of their respective external magnet ic fields. use a constant distance between the differential traces to avoid irregularities in differential impedance. avoid 90 turns (use two 45 turns). minimize the number of vias to further prevent impedance irregularities. table 5. function table input output in x + in x - out x v id +100mv h v id +100mv l as1153 ? open, undriven short, or undriven 100 parallel termination h as1157 ? open or undriven short lvds signals 107 lvttl/lvcmos data inputs lvttl/lvcmos data outputs 100 shielded twisted cable or microstrip pc board traces tx rx as1157 lvds receiver as1154 0.1f 0.001f +3.3v 0.1f 0.001f +3.3v
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 11 - 16 as1153, as1157 datasheet - applications cables and connectors supported transmission media include printed circuit board traces, backplanes, and cables. use cables and connectors with matched differential impedance (typically 100 ) to minimize impedance mismatches. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to magnetic field cancelin g effects. bal- anced cables pick up noise as common mode, which is rejected by the lvds receiver. avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. termination due to the high data rates of lvds drivers, matched termination will prevent the generation of any signal reflections, and redu ce emi. the as1157 has integrated termination resistors connected across the inputs of each receiver. the value of the integrated resis tor is speci- fied in table 3. the as1153 requires an external termination resistor. the termination resistor should match the differential impedance of the t ransmission line and be placed as close to the receiver inputs as possible. termination resistance values may range between 90 to 132 depending on the characteristic impedance of the transmission medium. use 1% surface-mount resistors. board layout the device should be placed as close to the interface connector as possible to minimize lvds trace length. keep the lvds and any other digital signals separated from each other to reduce crosstalk. use a four-layer pc board that provides separate power, ground, lvds signals, and input signals. isolate the input lvds signals from each other and the output lvcmos/lvttl signals from each other to prevent coupling. separate the input lvds signals from the output signals planes with the power and ground planes for best results. figure 20. propagation delay and transition time test circuit in x + 50 50 in x - out x c l pulse generator** * 50 required for pulse generator. ** when testing the as1157, adjust the pulse generator output to account for internal termination resistor. receiver as1153, as1157
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 12 - 16 as1153, as1157 datasheet - applications figure 21. propagation delay and transition time waveforms in x + in x - v ol out x v oh v id v id = 0 t thl t tlh t plhd t phld v id = 0 80% 50% 20% v id = (v in x + ) - (v in x - ) note: v cm = (v in- + v in+ ) 2 80% 50% 20%
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 13 - 16 as1153, as1157 datasheet - package drawings and markings 10 package drawin gs and markings figure 22. 8-pin soic marking table 6. packaging code xxxx xxxx encoded datecode
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 14 - 16 as1153, as1157 datasheet - package drawings and markings figure 23. 8-pin soic package diagram
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 15 - 16 as1153, as1157 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 7. note: all products are rohs compliant. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 7. ordering information ordering code marking description delivery form package as1153 as1153 dual lvds receiver tubes 8-pin soic AS1153-T as1153 dual lvds receiver tape and reel 8-pin soic as1157 as1157 dual lvds receiver, with termination tubes 8-pin soic as1157-t as1157 dual lvds receiver, with termination tape and reel 8-pin soic
www.austriamicrosystems.com/interfaces-lvds/as1153 revision 1.02 16 - 16 as1153, as1157 datasheet copyrights copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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